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Y-DELTA transform , star to delta transformation
User Rating: / 0
Electronics lessons - General electronics
Written by Bogdan   

Y-Δ transform

The Y-Δ transform, also written Y-delta, Wye-delta, Kennelly’s delta-star transformation, star-mesh transformation, T-Π or T-pi transform, is a mathematical technique to simplify the analysis of an electrical network. The name derives from the shapes of the circuit diagrams, which look respectively like the letter Y and the Greek capital letter Δ. In the United Kingdom, the wye diagram is known as a star.
 

 Basic Y-Δ transformation

Y and Δ circuits with the labels which are used in this article.
Y and Δ circuits with the labels which are used in this article.

The transformation is used to establish equivalence for networks with 3 terminals. Where three elements terminate at a common node and none are sources, the node is eliminated by transforming the impedances. For equivalence, the impedance between any pair of terminals must be the same for both networks. The equations given here are valid for real as well as complex impedances.

 

Equations for the transformation from Δ-load to Y-load 3-phase circuit

The general idea is to compute the impedance Ry at a terminal node of the Y circuit with impedances R', R'' to adjacent nodes in the Δ circuit by

R_y = \frac{R'R''}{\sum R_\Delta}

where RΔ are all impedances in the Δ circuit. This yields the specific formulae

R_1 = \frac{R_aR_b}{R_a + R_b + R_c},
R_2 = \frac{R_bR_c}{R_a + R_b + R_c},
R_3 = \frac{R_aR_c}{R_a + R_b + R_c}.

Equations for the transformation from Y-load to Δ-load 3-phase circuit

The general idea is to compute an impedance RΔ in the Δ circuit by

R_\Delta = \frac{R_P}{R_\mbox{opposite}}

where RP = R1R2 + R2R3 + R3R1 is the sum of the products of all pairs of impedances in the Y circuit and Ropposite is the impedance of the node in the Y circuit which is opposite the edge with RΔ. The formulae for the individual edges are thus

R_a = \frac{R_1R_2 + R_2R_3 + R_3R_1}{R_2},
R_b = \frac{R_1R_2 + R_2R_3 + R_3R_1}{R_3},
R_c = \frac{R_1R_2 + R_2R_3 + R_3R_1}{R_1}.

 Graph theory

In graph theory, the Y-Δ transform means replacing a Y subgraph of a graph with the equivalent Δ subgraph. The transform preserves the number of edges in a graph, but not the number of vertices or the number of cycles. Two graphs are said to be Y-Δ equivalent if one can be obtained from the other by a series of Y-Δ transforms in either direction. For example, the Petersen graphs are a Y-Δ equivalence class.

 Demonstration

 Δ-load to Y-load transformation equations

Let us know the values of Rb, Rc and Ra from the Δ configuration. We want to obtain the values of R1, R2 and R3 of the equivalent Y configuration. In order to do that, we will calculate the equivalent impedances of both configurations in N1N2, N1N3 and N2N3, supposing in each case that the omitted node is unconnected, and we will equal both expressions, since the resistance must be the same.

The resistance between N1 and N2 when N3 is not connected in the Δ configuration is

R(N_1, N_2) = R_b \parallel (R_a+R_c) = \frac{R_b(R_a+R_c)}{R_b+R_c+R_a} = \frac{R_bR_a+R_bR_c}{R_b+R_c+R_a}.

In the Y configuration, we have

R(N1,N2) = R1 + R2;

hence we have

R_1+R_2 = \frac{R_bR_a+R_bR_c}{R_b+R_c+R_a}   (1)

By similar calculations we obtain

R_2+R_3 = \frac{R_cR_a+R_cR_b}{R_b+R_c+R_a}   (2)

and

R_1+R_3 = \frac{R_aR_b+R_aR_c}{R_b+R_c+R_a}.   (3)

The impedances for the Y configuration can be derived from these equations by adding two equations and subtracting the third. For example, adding (1) and (3), then subtracting (2) yields

R_1+R_2+R_1+R_3-R_2-R_3 = \frac{R_bR_a+R_bR_c}{R_b+R_c+R_a} + \frac{R_aR_b+R_aR_c}{R_b+R_c+R_a} - \frac{R_cR_a+R_cR_b}{R_b+R_c+R_a}

and hence

2R_1 = \frac{2R_bR_a}{R_b+R_c+R_a}

and

R_1 = \frac{R_bR_a}{R_b+R_c+R_a}.

 Y-load to Δ-load transformation equations

Let RT = Ra + Rb + Rc. We can write the Δ to Y equations as

R_1 =  \frac{R_aR_b}{R_T}   (1)
R_2 =  \frac{R_bR_c}{R_T}   (2)
R_3 =  \frac{R_aR_c}{R_T}.   (3)

Multiplying the pairs of equations yields

R_1R_2 = \frac{R_aR_b^2R_c}{R_T^2}   (4)
R_1R_3 = \frac{R_a^2R_bR_c}{R_T^2}   (5)
R_2R_3 = \frac{R_aR_bR_c^2}{R_T^2}   (6)

and the sum of these equations is

R_1R_2 + R_1R_3 + R_2R_3 = \frac{R_aR_b^2R_c + R_a^2R_bR_c + R_aR_bR_c^2}{R_T^2}   (7)

Now we divide each side of (7) by R1, leaving

\frac{R_1R_2 + R_1R_3 + R_2R_3}{R_1} = \frac{1}{R_1}\frac{R_aR_b^2R_c + R_a^2R_bR_c + R_aR_bR_c^2}{R_T^2}.   (8)

Using (1) in (8), we have

\frac{R_1R_2 + R_1R_3 + R_2R_3}{R_1} = \frac{R_c(R_b + R_a + R_c)}{R_T}

and by definition of RT

\frac{R_1R_2 + R_1R_3 + R_2R_3}{R_1} = R_c

which is the equation for Rc. Dividing (7) by R2 and R3 gives the other equations.

References

  • William Stevenson, “Elements of Power System Analysis 3rd ed.”, McGraw Hill, New York, 1975, 

 External links


From Wikipedia, the free encyclopedia

 
60W DC/DC Converters in 51x51x10mm Package
User Rating: / 0
The News - Power News
Written by Sergiu   

60W DC/DC Converters in 51x51x10mm Package

 
TRACOPOWER launches with the TEN-60 series a new range
of isolated, high performance DC/DC converter modules.

8 models with output voltages of 3.3, 5.0, 12 and 15 VDC are available with 18-36 or 36-75VDC input voltage range. The product features 1500V I/O-isolation, under-/overvoltage lock-out, remote ON/OFF, adustable output voltage, short circuit and overvoltage protection and a built-in EMI filter. A very high efficiency up to 91% allows an extended operating temperature of –40°C to +85°C. All models comes in a shielded, ultra compact 51x51x10 mm(2”x 2”x 0.4”) metal package with isolated baseplate. The modules are lead-free and are fully RoHS compliant. Standard pricing is € 37.00 in 1000 off quantities.

 

The TEN 60 series is a family of high performance 60W dc-dc converter modules with
wide 2:1 input voltage ranges in a compact low profile case with industry-standard
footprint. A very high efficiency allows an operating temperature range of –40°C to
85°C. Built-in filters for both input and output minimizes the need for external filtering.
Further standard features include remote On/Off, output voltage trimming, over voltage
protection, under voltage lockout and short circuit protection.
Typical applications for these products are battery operated equipment and distributed
power architectures in communication and industrial electronics, everywhere where
isolated, tightly regulated voltages are required and space is limited on the PCB.

 

 Model Input voltage range Output voltage Output current max.Efficiency typ. 
 TEN 60-2410 18 – 36 VDC 3.3 VDC 14.0 A 89 %
 TEN 60-2411 18 – 36 VDC 5 VDC 12.0 A 89 %
 TEN 60-2412 18 – 36 VDC 12 VDC 5.0 A 90 %
 TEN 60-2413 18 – 36 VDC 15 VDC 4.0 A 90 %
TEN 60-4810 36 – 75 VDC 3.3 VDC 14.0 A 89 %
TEN 60-4811 36 – 75 VDC 5 VDC 12.0 A 90 %
 TEN 60-4812 36 – 75 VDC 12 VDC 5.0 A 90 %
 TEN 60-4813 36 – 75 VDC 15 VDC 4.0 A 90 %
     

 2007-03-18

 
PLL frequency synthesizer handles 8 GHz
User Rating: / 0
The News - Latest News and Articles
Written by Administrator   

Analog Devices integrated 8 GHz phase-locked loop frequency synthesizer is the RF Design Product of the Month for June 2006.

For the PDF version of this article, click here.

To simplify system design and cut costs in high-frequency wireless systems, Analog Devices has developed an integrated 8 GHz phase-locked loop (PLL) frequency synthesizer that eliminates the need for frequency doublers. Designed for wireless systems, such as those used for broadband wireless access, satellite communications, instrumentation, wireless LANs and base stations for wireless radio, the new ADF4108 is the highest-frequency PLL synthesizer currently available on the market, according to the manufacturer. The device can be used to implement local oscillators in the upconversion and downconversion sections of wireless receivers and transmitters. It consists of a low-noise digital phase frequency detector (PFD), a precision charge pump, a programmable reference divider, programmable A (6 bit) and B (13 bit) counters, and a dual-modulus prescaler (P/P +1). The A and B counters, in conjunction with the dual-modulus prescaler, implement an N divider (N = BP+A). In addition, the 14-bit reference counter (R counter) allows selectable REFIN frequencies at the PFD input. The ADF4108 has a power supply range of 3.2 V to 3.6 V and a separate charge pump supply (VP) allows extended tuning voltage in 3.3 V systems. A complete PLL can be implemented if the synthesizer is used with an external loop filter and voltage-controlled oscillator (VCO). Operating temperature range for the device is -40 °C to +85 °C.

 

Other features include a three-wire serial interface to control on-chip registers, hardware and software power-down mode, and loop filter design with ADIsimPLL. In fact, the manufacturer recently upgraded ADIsimPLL to version 3.0. The improved simulator offers a comprehensive PLL design and simulation package for ADI's range of PLL frequency synthesizers, enabling rapid prototype development and design optimization. ADIsimPLL version 3.0 is available free of charge as a download from ADI's web site, thereby allowing designers to run simulations locally.

Normalized phase noise floor of the PLL synthesizer is given at -219 dBc/Hz (typical). Hence, the phase noise performance of ADF4108 at 7.9 GHz is rated at -81 dBc/Hz (typ.) at 1 kHz offset and 1 MHz PFD. Implemented in 0.35 µm BiCMOS process, the ADF4108 is pin compatible with 6 GHz PLL synthesizer ADF4106. Power consumption is 60 mW.

It is available in a lead-frame chip-scale package (LFCSP) and is priced at $3.30 per unit in quantities of 1,000.

Analog Devices
Norwood, Mass.
800-262-5643

www.analog.com

 

 
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