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Home arrow Blog arrow Flip-flop circuits
Flip-flop circuits PDF Print E-mail
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Flip-flop circuits

In electronics and digital circuits, the flip-flop or bistable multivibrator capable of serving as a one- signals; a is a pulsed digital circuitbit memory. A flip-flop typically includes zero, one, or two inputclock signal; and an output signal, though many commercial flip-flops additionally provide the complement of the output signal. Some flip-flops include a clear input signal, which resets the current output. Because flip-flops are implemented as integrated circuit chips, they also require power and ground connections.

Pulsing, or strobing, the clock causes the flip-flop to either change or retain its output signal, based upon the values of the input signals and the characteristic equation of the flip-flop. Strobing here means changing the clock; some flip-flops change output on the rising edge of the clock, and other change on the falling edge.

Flip-flops can be split into two main categories: level-triggered and edge-triggered. They can further be divided into four types that have found common applicability in clocked sequential systems: these are called the T ("toggle") flip-flop, the SR ("set-reset") flip-flop, the JK flip-flop, and the D ("Data") flip-flop. The behavior of the flip-flop is described by what is termed the characteristic equation, which derives the "next" (i.e., after the next clock pulse) output, Qnext, in terms of the input signal(s) and/or the current output, Q.

The first electronic flip-flop was invented in 1919 by William Eccles and F. W. Jordan (Radio Review Dez 1919 pages 143 following). It was initially called the Eccles-Jordan trigger circuit. The name flip-flop was later derived from the sound produced on a speaker connected with one of the backcoupled amplifiers output during the triggerprocess within the circuit.


  • 1 Level-triggered flip-flops
    • 1.1 Set-reset flip-flops (SR flip-flops)
    • 1.2 D-type transparent latch
  • 2 Edge-triggered flip-flops
    • 2.1 Toggle flip-flops (T flip-flops)
    • 2.2 JK flip-flop
    • 2.3 D flip-flop
  • 3 Uses
  • 4 Timing and metastability
  • 5 Flip-Flop integrated circuits
  • 6 See also
  • 7 External links


Level-triggered flip-flops

Level-triggered flip-flops respond whenever a signal level changes.

Set-reset flip-flops (SR flip-flops)

The SR (set-reset) flip-flop has two inputs: S (set) and R (reset). If R is active, the output goes to zero. If S is active, the output goes to one. If neither is activated, the previous state is maintained. Both inputs should not be activated simultaneously; however, if they are, the typical response is for both the inverted and non inverted outputs to have the same level. The behavior of the flip-flop can be described by the characteristic equation: Q+ = S + R'Q.

The behavior of an SR flip-flop can written in the form of a truth table:

S R Qold Q
0 0 0 0
0 0 1 1
0 1 X 0
1 0 X 1
1 1 X implementation dependent
An SR flip-flop timing diagram.
An SR flip-flop timing diagram.

We can implement a the SR flip-flop with a pair of either NAND or NOR gates. The NOR version is conceptually easier as it has active high inputs. However, the NAND version is more widely known and used, as NAND gates were cheaper in transistor-transistor logic.

We can also easily add an enable input. If this is implemented in the same gates as the flip-flop, then it serves to further invert the inputs - meaning a NAND based device will now have active high inputs. This input may be regarded as a clock but the flip-flop is still unsuitable for sequential design. When the clock goes high, the signal will propagate through all flip-flops, not just from one to the next.

An SR flip-flop circuit diagram.
An SR flip-flop circuit diagram.
The symbol for an unclocked SR flip-flop
The symbol for an unclocked SR flip-flop
A clocked SR flip-flop constructed from NAND gates.
A clocked SR flip-flop constructed from NAND gates.
The symbol for a clocked SR flip-flop
The symbol for a clocked SR flip-flop

D-type transparent latch

If we add two NAND gates to an unclocked SR flip-flop as in the following diagram, we get a "D-type transparent latch". When enable is active, the output follows the input (the arrangement is "transparent"); when enable is low, the output is latched at what it was when enable was last high. Note: the image has an error: it shows AND gates instead of NAND gates.

   A D-type transparent latch   DInput   CEnable/clock   QOutput   Q'Inverse of Q
A D-type transparent latch
D Input
C Enable/clock
Q Output
Q' Inverse of Q


Edge-triggered flip-flops

Edge-triggered flip-flops only change state on a particular edge (rising, falling, or very occasionally both directions) of a designated clock signal.

Toggle flip-flops (T flip-flops)

A circuit symbol for a T-type flip-flop, where > is the clock input, T is the toggle input and Q is the stored data output.
A circuit symbol for a T-type flip-flop, where > is the clock input, T is the toggle input and Q is the stored data output.

If the T input is high, the T flip-flop changes state ("toggles") whenever the clock input is strobed. If the T input is low, the flip-flop holds the previous value. This behavior is described by the characteristic equation:

Q_{next} = T \oplus Q

(or, without benefit of the exclusive-OR operator, the equivalent:

Qnext = TQ' + T'Q

) and can be described in a truth table:

T Q Qnext
0 0 0
0 1 1
1 0 1
1 1 0
Timing of a real toggle flip-flop. 0, 1. left=clock, right=Q. Not shown: T=1. Note: Cables cross without connection.
Timing of a real toggle flip-flop. 0, 1. left=clock, right=Q. Not shown: T=1. Note: Cables cross without connection.


A toggle flip-flop composed of a single RS flip-flop becomes an oscillator, when it is clocked. To achieve toggling, the clock pulse must have exactly the length of half a cycle. While such a pulse generator can be built, a toggle flip-flop composed of two RS flip-flops is the easy solution.

JK flip-flop

JK flip-flop timing diagram
JK flip-flop timing diagram

The JK flip-flop augments the behavior of the SR flip-flop by interpreting the S = R = 1 condition as a "flip" command. Specifically, the combination J = 1, K = 0 is a command to set the flip-flop; the combination J = 0, K = 1 is a command to reset the flip-flop; and the combination J = K = 1 is a command to toggle the flip-flop, i.e., change its output to the logical complement of its current value. Setting J = K = 0 results in a D-type flip-flop.

A circuit symbol for a JK flip-flop, where > is the clock input, J and K are data inputs, Q is the stored data output, and Q' is the inverse of Q.
A circuit symbol for a JK flip-flop, where > is the clock input, J and K are data inputs, Q is the stored data output, and Q' is the inverse of Q.

The characteristic equation of the JK flip-flop is:

Q_{next} = J\overline Q + \overline KQ

and the corresponding truth table is:

J K Q Qnext
0 0 0 0
0 0 1 1
0 1 X 0
1 0 X 1
1 1 0 1
1 1 1 0

The origin of the name for the JK flip-flop is detailed by P. L. Lindley, a JPL engineer, in a letter to EDN, an electronics newsletter. The letter is dated June 13, 1968, and was published in the August edition of the newsletter. In the letter, Mr. Lindley explains that he heard the story of the JK flip-flop from Dr. Eldred Nelson, who is responsible for coining the term while working at Hughes Aircraft.

Flip-flops in use at Hughes at the time were all of the type that came to be known as J-K. In designing a logical system, Dr. Nelson assigned letters to flip-flop inputs as follows: #1: A & B, #2: C & D, #3: E & F, #4: G & H, #5: J & K. Given the size of the system that he was working on, Dr. Nelson realized that he was going to run out of letters, so he decided to use J and K as the set and reset input of each flip-flop in his system (using subscripts or somesuch to distinguish the flip-flops), since J and K were "nice, innocuous letters."

Dr. Montgomery Phister, Jr., an engineer under Dr. Nelson at Hughes, picked up the idea that J and K were the set and reset input for a "Hughes type" of flip-flop, which he then termed "J-K flip-flops," a name that he carried with him when he left for Scientific Data Systems in Santa Monica.

D flip-flop

A circuit symbol for a D-type flip-flop, where > is the clock input, D is the data input and Q is the stored data output.
A circuit symbol for a D-type flip-flop, where > is the clock input, D is the data input and Q is the stored data output.

The D-type ("Data") flip-flop takes one input, which it conveys to the output when the clock is strobed. Regardless of the current value of the output, it will assume a value 1 if D = 1 when the flip-flop is strobed or a value 0 if D = 0 when the flip-flop is strobed. This flip-flop can be interpreted as a primitive delay line or zero-order hold, since the data is posted at the output one clock cycle after it arrives at the input. It is called delay flip flop since the output takes the value in the Data-in.

The characteristic equation of the D flip-flop is:

Q_{next} = D \,

and the corresponding truth table is:

D Q > Qnext
0 X Rising 0
1 X Rising 1

The flip flops are very useful, as they form the basis for shift registers, which are an essential part of many electronic devices.

At the level of individual logic gates, the basic (without S and R) D-type flip-flop is made up of two D-type transparent latches arranged with a pair of inverters as below.

Note: this image also has an error: All the AND gates should be NAND gates.

Starting with a low signal on the clock, C, the signal at the input, D, is transferred through the first latch, as the inverted clock signal is high.

When the clock signal is made high, the inverted signal goes low, "locking" the signal at the output of the first stage. The doubly inverted signal now makes the second latch transparent and the signal is transferred through to the output Q (and Q').

When the clock goes low again, the output from the second stage (and therefore from the whole flip-flop) is locked in place, and the signal at D is transferred through the first stage, ready for the next strobing of the clock.

The advantage of this circuit over the D-type latch is that it is triggered by the rising edge of the clock, not the state, so it "captures" the signal at the moment the clock goes high, and subsequent changes of the data line do not matter, even if the signal line has not yet gone low again.

By removing the left-most inverter in the above circuit, a D-type flip flop that strobes on the falling edge of a clock signal can be obtained. This has a truth table like this:

D Q > Qnext
0 X Falling 0
1 X Falling 1

Most D-type flip-flops in ICs have the capability to be set and reset, much like an SR flip-flop. Usually, the illegal S = R = 1 condition is resolved in D-type flip-flops.

Inputs Outputs
S R D > Q Q'
0 1 X X 0 1
1 0 X X 1 0
1 1 X X 1 1

By settting S = R = 0, the flip-flop can be used as described above.


A single flip-flop can be used to store one bit, or binary digit, of data.

Static RAM, which is the primary type of memory used in registers to store numbers in computers and in many caches, is built out of flip-flops.

Any one of the flip-flop types can be used to build any of the others. The data contained in several such flip-flops may represent the state of a sequencer, the value of a counter, an ASCII character in a computer's memory or any other piece of information.

One use is to build finite state machines from electronic logic. The flip-flops remember the machine's previous state, and digital logic uses that state to calculate the next state.

The T flip-flop is useful for counting. Repeated signals to the clock input will cause the flip-flop to change state once per high-to-low transition of the clock input, if its T input is "1". The output from one flip-flop can be fed to the clock input of a second and so on. The final output of the circuit, considered as the array of outputs of all the individual flip-flops, is a count, in binary, of the number of cycles of the first clock input, up to a maximum of 2n-1, where n is the number of flip-flops used.

One of the problems with such a counter (called a ripple counter) is that the output is briefly invalid as the changes ripple through the logic. There are two solutions to this problem. The first is to sample the output only when it is known to be valid. The second, more widely used, is to use a different type of circuit called a synchronous counter. This uses more complex logic to ensure that the outputs of the counter all change at the same, predictable time.

Frequency division: a chain of T flip-flops as described above will also function to divide an input in frequency by 2n, where n is the number of flip-flops used between the input and the output.

Timing and metastability

A flip-flop in combination with a Schmitt trigger can be used for the implementation of an arbiter in asynchronous circuits.

Clocked flip-flops are prone to a problem called metastability, which happens when a data or control input is changing at the instant of the clock pulse. The result is that the output may behave unpredictably, taking many times longer than normal to settle to its correct state, or even oscillating several times before settling. Theoretically it can take infinite time to settle down. In a computer system this can cause corruption of data or a program crash.

In many cases, metastability in flip-flops can be avoided by ensuring that the data and control inputs are held constant for specified periods before and after the clock pulse, called the setup time (tsu) and the hold time (th) respectively. These times are specified in the data sheet for the device, and are typically between a few nanoseconds and a few hundred picoseconds for modern devices.

Unfortunately, it is not always possible to meet the setup and hold criteria, because the flip-flop may be connected to a real-time signal that could change at any time, outside the control of the designer. In this case, the best the designer can do is to reduce the probability of error to a certain level, depending on the required reliability of the circuit. One technique for suppressing metastability is to connect two or more flip-flops in a chain, so that the output of each one feeds the data input of the next, and all devices share a common clock. With this method, the probability of a metastable event can be reduced to a negligible value, but never to zero. The probability of metastability gets closer and closer to zero as the number of flip-flops connected in series is increased.

So-called metastable-hardened flip-flops are available, which work by reducing the setup and hold times as much as possible, but even these cannot eliminate the problem entirely. This is because metastability is more than simply a matter of circuit design. When the transitions in the clock and the data are close together in time, the flip-flop is forced to decide which event happened first. However fast we make the device, there is always the possibility that the input events will be so close together that it cannot detect which one happened first. It is therefore logically impossible to build a perfectly metastable-proof flip-flop.

Another important timing value for a flip-flop is the clock-to-output delay (common symbol in data sheets: tCO) or propagation delay (tP), which is the time the flip-flop takes to change its output after the clock edge. The time for a high-to-low transition (tPHL) is sometimes different from the time for a low-to-high transition (tPLH).

When connecting flip-flops in a chain, it is important to ensure that the tCO of the first flip-flop is longer than the hold time (tH) of the second flip-flop, otherwise the second flip-flop will not receive the data reliably. The relationship between tCO and tH is normally guaranteed if both flip-flops are of the same type.

Flip-Flop integrated circuits

Integrated circuit (ICs) can be found with one or two Flip-flop circuits on board. For example, the 7473 Dual JK Master-Slave Flip-flop or the 74374, an octal D Flip-flop, in the 7400 series.

External links

From Wikipedia, the free encyclopedia

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