Other features include a three-wire serial interface to control on-chip registers, hardware and software power-down mode, and loop filter design with ADIsimPLL. In fact, the manufacturer recently upgraded ADIsimPLL to version 3.0. The improved simulator offers a comprehensive PLL design and simulation package for ADI's range of PLL frequency synthesizers, enabling rapid prototype development and design optimization. ADIsimPLL version 3.0 is available free of charge as a download from ADI's web site, thereby allowing designers to run simulations locally.

Normalized phase noise floor of the PLL synthesizer is given at -219 dBc/Hz (typical). Hence, the phase noise performance of ADF4108 at 7.9 GHz is rated at -81 dBc/Hz (typ.) at 1 kHz offset and 1 MHz PFD. Implemented in 0.35 µm BiCMOS process, the ADF4108 is pin compatible with 6 GHz PLL synthesizer ADF4106. Power consumption is 60 mW.

It is available in a lead-frame chip-scale package (LFCSP) and is priced at $3.30 per unit in quantities of 1,000.

Analog Devices
Norwood, Mass.
800-262-5643
www.analog.com

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