Low power, giga speed programmable divider in 0.18 m CMOS

To meet the stringent low-power consumption and high-frequency operation at low switching noise of on-chip programmable dividers used in the design of PLL circuits, this article will focus on the design and simulation of a new programmable divider architecture for use in the 2.412 GHz to 2.484 GHz frequency bands. The design is based on 0.18 micron CMOS technology.

By comparison, the conventional programmable divider consists of a dual-modulus prescaler (DMP), a program (P) counter and a swallow (S) counter and is depicted in the block diagram shown in Figure 1. A DMP is used to get higher resolution. A DMP allows the prescaling factor to be changed between N and N+1. Prescaler divides 2.4 GHz down to the 75 MHz, which is used for the following loadable counters to minimize the silicon area and power. Here, a program counter acts as coarse tuner and a swallow counter as fine tuner. The counter/divider M is given as:

M = (N+1) S + N (P - S) = NP + S

For proper functioning of the counters, S should be smaller than P and S must also be less than N. The numbers of N, P and S should be chosen carefully according to the maximum limitation of the allowable input frequency of the counters.

The conventional design has the following issues:

• Requires two loadable down-counters.

• Reduces speed, due to delay introduced in the counter path.

• Increases design complexity while designing the loadable flip-flops.

• Reduces robustness of the circuit.

• Offers high power consumption at ~24 mW.

• Increases hardware and silicon area.

• 
  
  Prev - Next >>